Efforts are being made to stack chips or dice to increase performance without taking more space (e.g., more surface area) on a printed circuit board. This is particularly driven by requirements for sophisticated cell phones, smart phones, and other mobile devices. Chip makers have combined dynamic and static random access memory (DRAM and SRAM), flash and other memory in a connected integrated circuit structure or stack, but have historically been restrained by the added space requirements of wiring (e.g., wire bonding) that connects the chips. Chip or die stacking technology bonds two or more dies together to form a connected integrated circuit structure. The chips or dies may be connected together with interconnect wiring along the sides of the stack or metal vias at the die-die interfaces.
One common approach for chip or die stacking is referred to as face-to-face bonding. In this configuration, the device sides of, for example, two respective dies are stacked so that their device sides are facing one another and metal vias electrically connect the dies at the die-die interface. In one representation of a face-to-face bonded connected integrated circuit structure, a central processing unit (CPU) or logic die and a memory die (e.g., SRAM or DRAM die) are stacked together in a face-to-face bonding configuration. A heat sink may be attached to the bulk of the CPU or logic die and the power and input/output (I/O) connections to the package or circuit board are made with bump technology attached to the bulk of the memory die. Through-silicon vias (TSVs) may be used to pass through the memory die and connect to the metal die-to-die interface.
In the above example, since the through-silicon vias pass through the active silicon area of the memory of the second die (e.g., a memory die), sufficient area must be allocated in the circuitry to permit the through-silicon vias. These vias can typically be large (greater than 10 times) the minimum design rules for a given process due to power delivery requirements. Power for both dies is supplied by the through-silicon vias. Power requirements will dictate an approximately one through-silicon via per bump contact. In flip chip packaging, the bumps are usually arranged in a widely spaced uniform pattern across an entire two-dimensional die allowing for a high number of uniform power and ground connections at the top metal layer. This requires that the circuitry in the second die (e.g., memory die) be designed to accommodate these vias with proper spacing to adjacent geometries. This implies that the second die would need to be custom designed to exactly match the via requirements of the first die.
Another bonding configuration is a face-to-back bonding configuration. Using the example of a CPU die and a memory die, in a face-to-back bonding configuration, the position of the two die might be swapped. For example, the first die (CPU die) signal and power connections would be attached to the package in a typical way using standard bump technology. Power and signal connections for the second die (e.g., memory die) would pass through the first die using through-silicon vias. The power requirements of a memory die are usually much lower than a CPU or logic die and therefore the number of through silicon vias required to pass through the first die (e.g., CPU die) is considerably less and need not be uniformly spaced across the die. This makes the design and layout of a CPU die much less impacted by the three-dimensional bonding of a second die.